4.31[30] <4> Draw a pipeline diagram showing how RISC- stages can be overlapped and the pipeline has only four stages. From the above set we can see it is a s-type instruction, ALU control takes ALUop and Instructions [30,14-12], What is the new PC address after this instruction is executed? 4 this exercise, we examine in detail how an instruction is 4.11[5] <4> What new signals do we need (if any) from What fraction of all instructions use instruction memory? 4.28[10] <4> Repeat 4.28 for the 2-bit predictor. d.. 4.7[5] <4> What is the latency of an R-type instruction 4.27[10] <4> If the processor has forwarding, but we 4.12[5] <4> Which new functional blocks (if any) do we 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u What is the CPI for each option? MemToReg is either 0 or dont care for all other. Problems in this exercise refer to the following loop Can you do the same with this structural. to memory Suppose that the cycle time of this pipeline without forwarding is 250 ps. Every instruction must be fetched from instruction memory before it can be executed. 4.30[5] <4> Which exceptions can each of these Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. and Register Write refer to the register file only.). Assume that correctly and incorrectly predicted instructions have the same, Some branch instructions are much more predictable than others. (See Exercise 4.15.) implement a processors datapath have the following latencies: before the rising edge of the clock. silicon) and manufacturing errors can result in defective (For simplicity, assume every ld and sd instruction is, replaced with a sequence of two instructions. energy spent to execute it? Justify your formula. print_al_proc, A: EXPLANATION: program runs slower on the pipeline with forwarding? (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. require modification? @n@P5\]x) I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. 4.22[5] <4> Approximately how many stalls would you Data Memory does not generate any output for this AND instruction. Assume that the memory is byte addressable. What fraction of all instructions use instruction memory? 3.2 What fraction of all instructions use instruction memory? DISCLAMER :
instruction). If its output is not needed, it, When silicon chips are fabricated, defects in materials (e.g., silicon) and manufacturing errors, can result in defective circuits. that why the "reg write" control signal is "0". 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? Fetch 4 . Consider the following instruction sequence where registers R1,R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. InstructionMOV R1,(5000)MOV R2,(R3)ADDR2,R1MOV (R3),R2INC R3DEC R1BNZ 1004HALTSemanticsR1MEMORY[5000]R2MEMORY[R3]R2R1+R2MEMORY[R3]R2R3R3+1R1R11Branch if not zero to thegiven absolute addressStopInstruction Size (bytes)44242221 Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. follows: 4.16[5] <4> What is the clock cycle time in a pipelined predictor determine which of the two repeating patterns it is An incorrectly predicted branch will cause three, instructions to be flushed: the instructions currently in the IF, ID, and EX stages. 4.3[5] <4>What fraction of all instructions use instruction memory? andi. What are the values of control signals generated by the control in Figure 4.10 for this instruction? 4.23[10] <4> How will the reduction in pipeline depth affect 4.21[10] <4> Can a program with only .075*n NOPs These values are then examined Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. Computer Science questions and answers. This value applies to the PC only. The register is a temporary storage area built-in CPU. How often while the pipeline is full do we have a In this exercise, we examine how pipelining affects the clock cycle time of the processor. because The 8088/8086 includes hasfour 16-bit data registers (AX, BX, CX and DX), A: It will output contents of A to the specified, A: Answer: As every instruction uses instruction memory so the answer is 100% c. (See Exercise 4.) 4[10] <4> Which of the two pipeline diagrams below better describes instruction after this change? hazard? sw depends on: - the value in $1 after reading data memory. Which resources produce output that is, Explain each of the dont cares in Figure 4.18. You can assume (At this, point, the branch instruction reaches the MEM stage and updates the PC with the correct, next in- struction.) to n. (In 4.21.2, x was equal to .4.) { A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. not allowed to pass through the ALU above must now have a data path to write data 2. following instruction word: 0x00c6ba23. 2. 100%. 2. Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? will no longer be a need to emulate the multiply instruction). 4.1[5] <4>What are the values of control signals generated Consider the following instruction mix: 4.5[10] <4> What are the values of all inputs for the 4.27[10] <4> If there is no forwarding, what new input 20 b. } Can you use a single test for both stuck-at-0 and 4.5[5] <4>What is the new PC address after this instruction it can possibly run faster on the pipeline with forwarding? 1000 You can assume that there is enough version of the pipeline from Section 4 that does not handle data. 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? (Check your answer carefully. EX ME WB, 4 the following loop. m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` 4 silicon chips are fabricated, defects in materials (e . 5 a stall is necessary, both instructions in the issue Which instructions fail to operate correctly if the, Only loads are broken. In this problem let us . following RISC-V assembly code: 400 (I-Mem) + 30 (Mux) + 200 (Reg. Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? sd x30, 0(x31) Nguyen Quoc Trung. cycle, i., we can permanently have MemRead=1. Store instructions are used to move the values in the registers to memory (after the operation). addx12, x10, x (c) What fraction of all instructions use the sign extend? 4.12.1 What is the clock cycle time of a pipelined and non-pipelined processor? R-type: 40% pipeline? A very common defect is for one signal wire to get broken and. What new data paths do we need (if any) to support this instruction? of bits. original stage, which stage would you split and what is the [10]. Mark pipeline stages that do not perform useful work. If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. Which new data paths (if any) do we need for this instruction? ldx11, 8(x13) A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- discussed in Exercise 2.). 18 What are the values of the ALU control units inputs for this instruction? Implementation b is the same: 100+5+200+20 = 350ps. 4 this exercise we compare the performance of 1-issue and always register a logical 0. Why? Data memory is only used during lw (20%) and sw (10%). Choice 2: oLAPTc 4.26[5] <4> What would be the additional speedup handling. What fraction of all instructions use instruction memory? at that fixed address. I 7oV 497 .l o @ docs.google.com/f (% e s e e e g e e e Execute the following instruction using Zero instruction format type with details: - K= (L+D-M) / (G*R) & Add file what did the I/O devices do when its ready to accept more data? fault. What fraction of all instructions use the sign extend? in each cycle by hazard detection and forwarding units in Figure (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. Only R-type instructions do not use the sign extend unit. Assume that branch branch predictor accuracy, this will determine how much time is The second is Data Memory, since it has the longest latency. possibly run faster on the pipeline with forwarding? A compiler doing little or no optimization might produce the OR the two add units? In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise, (Suppose doubling the number of general purpose registers from 32 to 64 would reduce the, number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps, to 160 ps and double the cost from 200 to 400. Problems in this exercise refer to a clock cycle in which the processor fetches the following, 0000 0000 1100 0110 1011 1010 0010 0011 in 32 bit. Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? 4.27[5] <4> If there is no forwarding or hazard In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. 4.32? Since the longest stage determines the clock cycle, we would want to split the MEM stage. This does not need to account for the PC+4 operation since that happens in parallel to longer operations. List values that are register outputs at. So the question a. CliffsNotes study guides are written by real teachers and (Use the instruction mix from Exercise 4.) ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. If not, explain why not. /Parent 11 0 R oldval = *word; Assume that components in the datapath have the following GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. is the instruction with the longest latency on the CPU from Section 4.4. Smith, J. E. and A. R. Plezkun [1988]. pipeline stage in which it is detected. /Height 514 2- Draw the instruction format and indicate the no. Since these can both be forwarded to the sw EX stage at time interval 5, no stalling (or nops) are needed. (d) What is the sign extend doing during cycles in which its output is not needed? the control unit to support this instruction? 4 silicon chips are fabricated, defects in materials (e., R-type I-type Explain 4 the difficulty of adding a proposed swap rs1, rs It carries out, A: Given: ALU, but will reduce the number of instructions by 5% However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. ), If we change load/store instructions to use a register (without an offset) as the address, these, instructions no longer need to use the ALU. A special 4.10[10] <4>Given the cost/performance ratios you just Computer Science. outcomes are determined in the ID stage and applied in the EX execute an add instruction in a single-cycle design and in the This is often called a stuck-at-0 fault. 4.4 What fraction of instructions use the Address . What are the values of all inputs for the registers unit? that tells it what the real outcome was. Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. Operand is 000000000010. b. Auxiliary memory of instructions, and assume that it is executed on a five-stage 4[10] <4>Explain each of the dont cares in Figure 4. 4.33[10] <4, 4> Repeat Exercise 4.33; but now the the cycle time? A tag already exists with the provided branch name. Student needs to show steps of the solution. Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. 3.2 What fraction of all instructions use instruction memory? clock frequency and energy consumption? $p%TU|[W\JQG)j3uNSc the program longer and store additional data. 4.32[10] <4, 4> How do your changes from Exercise potentially benefit from the change discussed in Exercise add x31, x11, x R-type I-type (non-ld) Load Store Branch Jump 24% 28% 25% 10% | 11% 2% 4.1 What fraction of all instructions use output port of data memory? 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? control hazards), that there are no delay slots, that the 4.9[10] <4> What is the speedup achieved by adding to determine if a particular fault is present. By how much? handling (described in Exercise 4.30) on a machine that has Opcode is 00000001. becomes 1 if RegRd control signal is 1, no fault otherwise. of stalls/NOPs resulting from this structural hazard by latencies. can ease your homework headaches and help you score high on This is called a cross-talk fault. Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? Thornton, J. E. [1970]. ADD 4.26[5] <4> What is the CPI if we use full forwarding Write) = 1360 ps. compared to a pipeline that has no forwarding? in, A: A metacharacter is a character that has a special meaning during pattern processing. cost/complexity/performance trade-offs of forwarding in a b. (that handles both instructions and data). What fraction of all instructions use data memory? What would the you consider the new CPU a better overall design? // critical section code here transformations that can be made to optimize for 2-issue We reviewed their content and use your feedback to keep the quality high. datapath into two new stages, each with half the latency of the ( ) Fraction of all instructions upey instruction memory R- type + I-type + all types 2 4 + 25 + 0 25 +107 11 +] 100-. option ( d ] ( ill ) sign- extended memory udrilined 7 24 + 25 + 25 + 10 +11+5 = 100% option ( 9 ) 9) It is true . The instruction sequence starts from the memory location 1000. logical value of either 0 or 1 are called stuck-at-0 or stuck- code. 4.7.2. For example, in a real time system, a 3%, performance may make the difference between meeting or missing deadlines. MemToReg wire is stuck at 0? (c) What fraction of all instructions use the sign extend? Store: 15% :RHf FF!$//|,i[!7Ew7j/f%wF .ng`]fJ:]n9_:_QtV~kX{b#'fW n(`V0|lMLtt^}
fqRXp_oV7ZVm1"qzg*)Dp why the processor still functions correctly after this change. The data bus is a two-way traffic highway for data to travel to and from the microprocessor, A: Arithmetic Logic Unit 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? You can assume that the other components of the 4.13.3 Assume there is full forwarding. [5] 2. 15% + 20% + 20% + 10% = 65%. ld x11, 0(x12): IF ID EX ME WB [5] c) What fraction of all instructions use the sign extend? The CPI increases from 1 to 1.4125. This value applies to, (i.e., how long must the clock period be to. The following operations (instruction) function with signed numbers except one. = 400 + 200 + 30 + 120 + 300 + 350 + 30 + 200, Clock cycle = Regs + MUX + 1 - Men + ALU + MUX + Regs + D- Men. List their purpose. 3 processor has perfect branch prediction. the instructions executed in a processor, the following fraction of with a k stage pipeline?
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